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AN713 vishay siliconix document number: 70584 www.vishay.com faxback 408-970-5600 1 a 1-watt flyback converter using the si9100 the si9100 is a monolithic bic/dmos smartpower ic which combines high-efficiency cmos logic, a high-voltage switching transistor and high-voltage pre-regulator on a single die. it is the first low-cost, high efficiency regulator designed to operate directly from unregulated high-voltage dc power sources in areas such as telecommunications and avionics. the primary application will be in feature phones and isdn terminals to power the logic components without exceeding the load limits set by the telecommunications industry. power integrated circuit technology allows low-power cmos control circuits to be combined with dmos power transistors in the si9100. the resulting reduced parts count decreases system cost, improves reliability, and simplifies circuit design. the flyback converter presented here uses the si9100 to provide an isolated 5-v supply rated at 1 w. specifications for this supply are as follows: input voltage 15 to 70 v dc . . . . . . . . . . . . maximum load +5 v @ 167 ma, . . . . . . . . . . . 5 v @ 33 ma minimum load +5 v @ 32 ma, . . . . . . . . . . . 5 v @ 8 ma regulation 5% . . . . . . . . . . . . . . maximum ripple 100 mv p-p . . . . . . . . . switching frequency 100 khz . . . . . . efficiency 80% min for 1 w load . . . . . . . . . . . . . . . 75% min for 0.2 w load a schematic for the flyback converter is found in figure 1, with a parts list provided in appendix b. however, before discussing the details of the power supply design, it is instructive to review the functions of the si9100 integrated circuit. 240 k c4 0.022 f figure 1. schematic diagram of the si9100 discontinuous flyback converter circuit + + + l1 1n5819 cr2 cr3 +5 v 5 v output 1n5819 input gnd (gnd plane) 2 3 4 5 6 7 8 9 10 11 12 13 14 1 si9100 cri 1n4148 u1 100 h r3 150 k r1 390 k r2 1 0.5 w r5 18 k r6 12 k r4 c3 0.1 f c5 1 f c2 0.1 f c1 20 f c6 0.1 f c8 0.1 f c7 100 f c9 20 f l2 ns1 = 8 ns2 = 8 ns3 = 16 np = 21 150 h nc nc
AN713 vishay siliconix www.vishay.com faxback 408-970-5600 2 document number: 70584 + + + + + fb comp discharge osc 14 (20) 13 (18) 9 (12) 8 (11) 7 (10) 2 v ref gen r s q r s q drain source 3 (5) 5 (8) 4 (7) 11 (16) 12 (17) current-mode comparator c/l 1.2 v undervoltage comparator reset 8.1 v 8.6 v bias current sources to internal circuits 10 (14) 1 (2) 6 (9) 2 (3) comparator error amplifier v ref v cc +v in v cc shutdown 4 v (1%) osc out osc in note: figures in parenthesis represent pin numbers for 20-pin package. v in (body) clock ( 1 / 2 f osc ) figure 2. si9100 simplified block diagram
as shown in the block diagram of figure 2, the si9100 combines an oscillator, pre-regulator/start-up circuit, precision voltage reference, error amplifier, current-mode controller, and a mosfet switching transistor into one 14-pin dual-in-line package. overcurrent protection, undervoltage lockout, and logic inputs for both latched and unlatched shutdown modes are also included. start-up/preregulator circuit a unique start-up/preregulator circuit, which is shown in figure 3, permits the si9100 to operate over a wide input voltage range (10 to 70 v). the input voltage for the device is connected between the +v in (pin 2) and v in (pin 5) terminals. the high-voltage depletion-mode (normally on) mosfet acts as a current source during start-up, charging the capacitance at the v cc terminal (pin 6) directly from the input source. when v cc exceeds the 8.1 v undervoltage threshold, the output switch is enabled to provide well-defined start-up characteristics. v cc is then regulated to 8.6 v by the pre-regulator circuit. if an external voltage source greater than 8.6 v is fed to the v cc terminal, the depletion-mode mosfet is shut off to reduce power drain from the input power source. oscillator the oscillator requires a single resistor to set its frequency. the requirements of flux reset in single-ended converters generally dictates a maximum duty cycle of 50%. with the oscillator frequency set at two times the desired switching frequency, a flip-flop divides the clock signal by two, and the logic disables the output during every other clock cycle. figure 3. schematic diagram of the start-up section of the si9100 8.6 v v cc +v in v in
AN713 vishay siliconix document number: 70584 www.vishay.com faxback 408-970-5600 3 mosfet switch the mosfet switching transistor has typical r ds(on) and v (br)dss characteristics of 4 and 180 v, respectively. worst case specifications are 5 and 150 v. the device is a lateral dmos structure which has external connections for the drain (pin 3) and source (pin 4). the body of the mosfet is internally tied to the v in terminal, which must be connected to the most negative input potential in the circuit. error amplifier the error amplifier permits compensation of control loops for stable regulator operation. the amplifier uses pmos input transistors to provide high input impedance (2 m minimum), and is internally compensated for unity gain stability, with 1 mhz (typical) bandwidth and 60 phase margin. protection in addition to the undervoltage lockout function already described, the si9100 provides overcurrent protection and inputs for external logic control. with a sense resistor (typically 1 to 2 ) connected from the mosfet source to the v in terminal, the voltage at pin 4 is proportional to the output current. when this voltage exceeds a 1.2 v reference the overcurrent comparator disables the output mosfet. the shutdown delay is typically 100 ns (200 ns maximum). logic inputs shutdown (pin 11) and reset (pin 12) permit the use of latched or unlatched shutdown modes. internal current source pull-ups normally hold both logic pins high. if the shutdown pin is pulled low while the reset is high, then the output switch will be disabled until the shutdown pin is again allowed to go high. this is the unlatched shutdown mode. if, however, the reset pin is pulled low while the shutdown pin is also pulled low, then the converter will be latched off until reset goes high again.

start-up applying input voltage to the circuit initiates charging of capacitor, c 1 , through the filter inductor, l 1 . the depletion-mode mosfet, as described above, supplies current to capacitor c 5 through the v cc terminal of the ic. when v cc reaches the undervoltage threshold (8.1 v), then transistor switching begins. the 4 v reference and the voltage divider ratio formed by r 5 and r 6 cause the feedback winding, n s3 , to be regulated to +10 v. after start-up is complete the feedback voltage trips the comparator to turn off the pre-regulator circuit, and the si9100 derives its bias power from the feedback winding. the power saved by this bootstrap technique is equal to the product of the ic supply current times the difference between v in and v fb : power saved = (600 a) (48 v 10 v) = 23 mw while this is not a great deal of power, it does represent 2.3% of the output for a 1 w supply. integrated services digital network (isdn) applications require such techniques for bias power minimization in order to meet emergency-mode limits for the power-down state. flyback operation flyback converter operation is illustrated by the basic waveforms shown in figure 4. when the mosfet switch is turned on, current will ramp up in the primary at a rate given by: figure 4. flyback converter waveforms i pk i pri i sec v pk v ds v in t on t rec t s di dt i pk t on v l == stored energy, given by 1 / 2 l p i pk 2 , is present in l 2 at the time the mosfet is switched off. this energy is released to the secondary windings, n s1 through n s3 , during the off time, as shown by the total secondary current, i sec , in figure 4. this is the flyback principle in its simplest terms. a transformer is designed to transfer energy directly from the primary to the secondary, with as little stored energy as possible. a flyback inductor receives energy during one interval of the switching cycle, then releases this stored energy at a later interval of the switching cycle. during the time that the secondaries are conducting, shown as t rec , the magnetic flux recovers, or aresetso to zero, and the mosfet must block the sum of the reflected voltage from the secondary and the input voltage. this requires a worst case blocking voltage of: v pk v in n p n s1 (v o v d ) 70 21 8 (5.0 0.5) 85 v
AN713 vishay siliconix www.vishay.com faxback 408-970-5600 4 document number: 70584 a leakage inductance spike appears at the leading edge of the v ds waveform. the spike is less than the 150 v minimum v (br)dss , and no snubber network is required. since the flux is reset to zero before the end of each switching cycle, current flow through the secondary is discontinuous. consequently, this circuit is called a disc ontinuous-conduction-mode (dcm) flyback converter. regulator control loop the function of the regulator control loop is to maintain the output voltages constant as either the input line voltage or load current vary. these are termed aline regulationo and aload regulationo, respectively. a sense winding has been chosen to close the regulator loop and provide output isolation. since the secondary windings are coupled on a common core, the volts/turn ratio is the same for n s1 , n s2 and n s3 . the resulting secondary voltages will track each other quite closely. there is, however, some degradation in load regulation due to leakage (uncoupled) inductance between the 1 / 2 5-v output windings and the sense winding. this effect becomes progressively worse as the switching frequency is increased. the coupled inductor used here has been designed for good coupling between output and sense windings in order to maintain better than 5% regulation over the 0.2 w to 1 w load range. design details for the coupled inductor are included in appendix a. to analyze the system closed loop response, begin by reflecting the filter capacitance and load resistance from each output winding to the feedback winding. c eff c 5 n s1 n s3 x c 7 c 9 1 f 8 16 2 (100 f 20 f) 31 f the effective load resistance, r eff , can be found by assuming that the entire 1-w load is connected across the sense winding output: r eff v 2 s p o (10 v) 2 1w 100 the effective load impedance is determined at low frequency by the 100 resistance and at high frequency by the capacitive reactance given by x c = 1/ c eff . the control-to-output transfer function thus has a pole at: f p 1 2 r eff c eff 1 2 (100)(31 x 10 6) 51 hz to calculate the low frequency gain of the power stage, assume a 1 mv change in the error voltage, v e , at the output of the error amplifier, and calculate the voltage change, v s , which results at the feedback winding. then combine the power stage gain with the error amplifier gain (including the voltage divider) to yield the total loop response. assume for these calculations that the converter efficiency remains constant at 83.33%. p in p 0 1w 0.8333 1.2 w the power input to the converter is the product of the stored inductive energy times the switching frequency.
rearranging to solve for i pk gives: i pk 2p in l p xf s 2(1.2) w (150 h) 10 5 hz 0.4 a since the current sense resistor, r 2 , equals 1 , a 1 mv change in the error voltage (at pin 13) will result in a 1 ma change in the peak inductor current, i.e., i pk = v e . a 1 ma increase in i pk causes p in to increase to: p in = 1 / 2 l p (i pk + di pk ) 2 s f s = 1 / 2 150 s 10 6 (0.400 + 0.001) 2 10 5 = 1.206 w assuming efficiency remains constant, p o = (0.833) p in = 1.005 w this translates to an increase in the sense voltage to: v s p o xr eff ( 100 x 1.005 ) 10.025 v the gain is given by: v s v e 10.025 v 10 v 1mv 25 at full load the low frequency gain of the power stage is 25 (28 db), with a single pole in the transfer function at 51 hz. performing a similar calculation at the 20% load condition yields a gain of 56 (35 db) with a pole at 10 hz. there will also be a zero in the transfer function at approximately 30 khz due to capacitor esr. the solid line in figure 5 represents the transfer function of the converter power stage at full load. the corresponding curve at a 20% load is shown in figure 6. to complete the analysis of the control loop requires accounting for the resistive voltage divider and the error amplifier. the resistor r 6 sets the dc bias condition, but does not enter into the small signal analysis.
AN713 vishay siliconix document number: 70584 www.vishay.com faxback 408-970-5600 5 1 frequency (hz) 80 60 40 20 0 20 40 10 100 1 k 10 k 100 k gain (db) 80 60 40 20 0 20 40 1 frequency (hz) 10 100 1 k 10 k 100 k gain (db) 100 mv 200 s figure 5. loop gain at 100% load figure 6. loop gain at 20% load figure 7. step load response at high frequencies the gain is r 4 /r 5 , with a zero occurring in the transfer function at f z 1 2 (240 k ) (0.022 f) 30 hz the error amplifier response is shown in figures 5 and 6 as dashed lines. the error amplifier response times the power stage gain gives the total loop gain, which is shown as the gray line for full load in figure 5 and light load in figure 6. actual measurements of loop gain and phase yielded a loop bandwidth of 14 khz with 68 degrees phase margin. figure 7 shows the response of the +5-v output as the load is stepped between 20% and 100% of full load. response time is under 200 s with no overshoot.
integrated services digital network (isdn) poses some unique problems to telecom systems design engineers. standards proposed by the international telephone and telegraph consultative committee (ccitt) recommend that input power to isdn terminal equipment (te) meet the limits outlined in table i 1 .
operating mode maximum input power to te efficiency target normal-active 900 mw 70% normal-power down 100 mw 60% emergency-active 400 mw 70% emergency-power down 25 mw 40%
AN713 vishay siliconix www.vishay.com faxback 408-970-5600 6 document number: 70584 the 25-mw limit during emergency power-down mode operation may be especially troublesome 2 . in order to supply 10 mw to the te for such functions as memory back-up, total converter losses must be less than 15 mw. under such light load conditions the major power loss is in the pwm controller. only controllers implemented in cmos can presently be expected to meet this requirement. although the converter circuit of figure 1 was not designed specifically for use in isdn terminals, with some modifications it can be used in these applications. since cmos logic circuits consume power only during switching transitions, the first modification which is recommended is to decrease the switching frequency. the coupled inductor, l 2 , can be operated at 40 to 50 khz (change r 3 from 150 k to 390 k ) without a redesign. decreasing the frequency further requires a larger core size. a second circuit modification which is recommended is to increase the resistances used in the voltage divider network (r 5 and r 6 ). the values used in the 1 w converter will dissipate (10) 2 /(18 k + 12 k ) = 3.33 mw. this loss is negligible for the 1 w converter, but it is nearly one fourth of the budgeted power loss for the isdn supply during the emergency power-down state. setting r 5 = 51.1 k and r 6 = 34.0 k reduces the voltage divider dissipation to 1.2 mw. with these two minor changes the flyback converter meets the efficiency specifications of table i. figure 8 illustrates the efficiency improvement at light load levels which results from the circuit changes outlined above.
the si9100 has been called a aone watt high-voltage switchmode regulatoro in order to describe its most appropriate type of application--low power converters. the device is not, however, limited to 1 w designs. figure 9 shows the maximum achievable output power as a function of minimum input voltage for several types of converters, two of which are discussed below. ccm flyback converter by redesigning the magnetics for continuous conduction, the flyback circuit of figure 1 can be made to provide 3 w of output power. operation in the continuous conduction mode (ccm) introduces a right-half-plane (rhp) zero into the control-to-output transfer function of the power stage. the rhp zero incurs a phase lag without the corresponding gain rolloff caused by left-half-plane poles, and lead compensation cannot be used. instead, the gain must be rolled off to unity (0 db) below the rhp zero frequency. the continuous-mode flyback will, therefore, have a slower dynamic response than the dcm flyback. also, to maintain the same output ripple for the 3 w converter, it is necessary to increase the size of the output filter capacitors. forward converter forward converters are not normally used for power supplies rated under 50 w, due to the additional cost of the output filter chokes. however, for 2- to 4-w converter applications requiring ultra-low ripple, the cost of the additional inductor may be warranted. one such application is low power instrumentation for avionics. the forward converter of figure 10 was designed to operate from 28-v aircraft power (mil-std-704d) to provide 2.5 w at 80% efficiency. a single core with multiple windings has been used to decrease cost and board space required for the output filter inductors. the input voltage range is 18 to 32 v dc ; regulation is 5%; and the switching frequency is 100 khz. measured peak-to-peak voltage ripple was 8 mv for the +15-v output, 4 mv for the 15-v output, and 13 mv for the +5-v output, at maximum load. 0 2 4 6 8 10 10 20 30 40 50 60 output power (w) 100 khz 45 khz figure 8. efficiency vs. load curves for the flyback converter 100 80 60 40 20 0 efficiency (%) 0 0.2 0.4 0.6 0.8 1 input voltage (v) dcm flyback boost figure 9. maximum output power vs. minimum input voltage ccm flyback and forward output power (w)
AN713 vishay siliconix document number: 70584 www.vishay.com faxback 408-970-5600 7 figure 10. 2.5-w forward converter using the si9100 11 12 2 3 4 10 15 9 13 14 6 8 7 si9100 nc nc +28 v mil-std-704) 28 vdc rtn 5 v rtn 15 v rtn +5 v +15 v 15 v 5 k 15 k 15 k 0.1 0.1 0.1 0.1 0.1 220 f 10 v 15 f 50 v 15 f 50 v 1 f 50 v 22 f 50 v 6 ea. 1n5806 1n4148 n3 n4 n4 n5 n1 n2 t1 (768t188-3c8 core) l2 (magnetics 55120 core) 1n4148 150 k 10 m 15 k 10 k 267 k 0.022 360 k 0.01 f 1 0.5 w l1 50 h toroidal cores were used for both the transformer and the coupled output inductor to achieve very low leakage inductance. the transformer winding data is as follows: core - ferroxcube #768t188-3c8 windings - n1 = 31 turns (awg26) n2 = 31 turns (awg34) n3 = 22 turns (awg32) n4 = 64 turns (awg32) n5 = 43 turns (awg34) the primary and clamp windings are placed on the core first, wound bifilar to minimize leakage inductance. the +5-v output is wound next, followed by the 15-v outputs wound bifilar. the 10-v winding was placed on the outside. each winding is spread over the entire circumference of the toroidal core for optimum magnetic coupling. coupled inductors must have the same turns ratios as the transformer secondaries or high circulating currents result in very high output ripple. the coupled inductor, l 2 , is a molypermalloy powder (mpp) toroid (magnetics #55120) with three times the number of turns as each of the t1 secondaries. the inductor winding data is as follows: +5 v 66 turns (awg30) +15 v 192 turns (awg30) 15 v 192 turns (awg34) +10 v 129 turns (awg34) it should be mentioned here that mil-std-461 emi testing was not performed for this supply. to meet ce03 and cs01 limits, some input filter redesign is required. although current-mode control exhibits excellent audio-susceptibility performance, it is still necessary to damp the input filter to reduce peaking of its output impedance at the resonant frequency (reference 3 provides useful design information regarding these requirements). references 1) rosenbaum, d. and stolp, k. h., athe feeding conception of the isdn basic access,o ieee intelec conference, munich, frg, oct 14-17, 1985, pp. 505-512. 2) krautkramer, w. and schickling, b., aremote power feeding of isdn terminals at the basic access,o ieee intelec conference, munich, frg, oct 14-17,1985, pp. 513-519. 3) middlebrook, r. d., ainput filter considerations in design and application of switching regulators,o ieee industry applications society annual meeting, oct. 11-14, 1976.
AN713 vishay siliconix www.vishay.com faxback 408-970-5600 8 document number: 70584

inductance calculation the first step is to calculate the maximum primary inductance for discontinuous conduction at maximum load. input power to the coupled inductor is approximately: (1) p in 1w 0.8 1.25 w input power is also equal to the product of the stored energy in the magnetic field times the switching frequency: (2) " the minimum primary current slope occurs at the minimum input voltage condition. di dt min v in(min) l p(max) if a maximum duty ratio of 0.45 is assumed, then the minimum current peak is given by: or (3) i pk di dt min x0.45t s #!#
# combining equations 2 and 3 gives: l p(max) 1 2 v in(min) 2 p in(max) x 0.45 t s 2 f s 1 2 l p(max) v in(min) l p(max) 2 0.45 t s 2 f s p in(max) 1 2 l p(max) i 2 pk(min) xf s 1 2 v in(min) 2 l p(max) x 0.45 t s 2 f s 1 2 (15) 2 1.25 x (0.45 t s ) 2 10 5 182 h to allow for component tolerances choose a nominal primary inductance of 150 h. equation 2 then gives i pk 0.4 a. core selection the area product method was used to determine the inductor core size. refer to amagnetic core selection for transformers and inductorso by mclyman, for more information on magnetics design methods (marcel dekker, inc., 1982). where: e = core energy storage requirement b m = maximum flux density k u = window utilization factor k j = current density coefficient e = l p i pk 2 let b m = 1500 gauss = 0.15 tesla, and k u = 0.10 = 0.0233 cm 4 a p 2ex10 4 b m xk u xk j 1.14 a p 2x 1 2 x 150 x 10 6 (0.4) 2 10 0.15 (0.10) (433) 1.14 since the empirical equation given above applies for the area product of simple one-winding inductors, multiply by 2 for a coupled inductor. all of the secondaries combined will handle the same energy as the primary, and can therefore be allotted equal portions of the window area. the area product requirement is thus: the ep-13 core has an area product of 0.049 cm 4 , which meets this requirement. also, this ep core can be tube-loaded for automatic insertion in high volume manufacturing applications, and is available from multiple sources (siemens, tdk, and amperex ferroxcube). core a l value determination the number of primary turns is found from: l n p i pk n p b m a c i pk limiting the peak flux density to 0.15 tesla gives:
n p l p i pk b m a c (150 10 6 )(0.4) 10 4 (0.15)(0.195 cm 2)
AN713 vishay siliconix document number: 70584 www.vishay.com faxback 408-970-5600 9 this gives the following value for a l : a l 1000 21 2 (150 10 6 ) 340 mh per 1000 turns secondary turns calculation the core flux is reset to zero during the off time for each switching cycle. to guarantee discontinuous conduction mode at the maximum load condition, it is necessary to limit the inductance of the secondary windings to some maximum value. worst case conditions occur at the maximum switching frequency (110 khz) and maximum a l value (374 mh/1000 turns for 10 % tolerance). the voltage across n s1 during the diode conduction interval is v o + v d = 5.0 + 0.5 = 5.5 v, and the negative current slope is di dt i s1 d rec v o v d l s1 where i s1 is the peak current in the n s1 winding, t rec is the conduction time of cr2, and l s1 is the inductance of n s1 . the rectifier conduction duty ratio is defined as: d r t rec t s the load current is related to the peak secondary current and duty ratio by the equation: i si 2 i o d r combining these equations solves for the rectifier conduction duty ratio in terms of load current, inductance, and output voltage. d r 2 i o l si (v o v d ) t s setting the duty ratio < 0.45 gives: d r 2 0.167 l s1 5.5 9.09 10 6 0.45 therefore, l s1 < 30.3 h. since al (max) = 374 mh/1000 turns,

use n s1 = n s2 = 8 turns: n s3 = (10 v + 0.7 v) 2 l s1 n s1 5.5 v n s1 5.5 v winding order the primary winding (1-2) is placed first over the bobbin using one strand of awg31 magnet wire (21 turns). the highest current secondary (3-4) is wound over the primary using two strands of awg31 (8 turns). the 10-v sense winding (7-8) is put down next, using one strand of awg36 (16 turns). the 5-v output (5-6) is wound last using one strand of awg31 wire (8 turns).
AN713 vishay siliconix www.vishay.com faxback 408-970-5600 10 document number: 70584

u1 si9100 . . . . . . . . . . . . . . . . . . . l1 inductor, 100 h @ 75 ma dc, vishay dale isc-1210 100 h 10% . . . . . . . . . . . . . . . . . . . . l2 coupled inductor, gfs mfg. # 85-787-4* gfs manufacturer . . . . . . . . . . . . . . . . . . . . c1 20 f, 100 v, aluminum electrolytic, vishay sprague # 30d+te1409 . . . . . . . . . . . . . . . . . . . c2, c3, c6, c8 0.1 f ceramic, vishay vitramon vj 1206y104kxxat . . . . . . . . . c4 0.022 f ceramic, vishay vitramon vj 1206y223kxxat . . . . . . . . . . . . . . . . . . . c7 100 f, 10 v, tantalum, vishay sprague # 199d107x9010p . . . . . . . . . . . . . . . . . . . c9 20 f, 10 v, tantalum, vishay sprague # 199d226x9010j . . . . . . . . . . . . . . . . . . . c5 1 f, 50 v, wima mks2 . . . . . . . . . . . . . . . . . . . cr1 1n4148 . . . . . . . . . . . . . . . . . . cr2, cr3 1n5819, schottky rectifier . . . . . . . . . . . . . r1 390 k , 1 / 4 w carbon . . . . . . . . . . . . . . . . . . . r2 1 , 1 / 2 w carbon . . . . . . . . . . . . . . . . . . . r3 150 k , 1 / 4 w carbon . . . . . . . . . . . . . . . . . . . r4 240 k , 1 / 4 w carbon . . . . . . . . . . . . . . . . . . . r5 18 k , 1 / 4 w carbon . . . . . . . . . . . . . . . . . . . r6 12 k , 1 / 4 w carbon . . . . . . . . . . . . . . . . . . . * gfs manufacturing company, 21 crosby road, dver, nh, usa 03820-1409

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